Quaternary 16X1 Multiplexer Design by using CMOS Multivalue Logic

Select Volume / Issue:

• Volume 4,Issue 1, Jan. 2016

Year:

2016

Type of Publication:

Article

Keywords:

MVL, Ternary Logic, Quaternary Logic, 16X1 multiplexer, Transmission Gate

Authors:

Md. Irshad Alam; Ruby Awasthi; Dr. Rita Jain

Journal:

IJISM

Volume:

4

Number:

1

Pages:

1-4

Month:

January

ISSN:

2347-–9

Abstract:

The circuits design using CMOS logic with large number of transistotors and maximum length interconnect are gradually more prevailing contributor to propagation delay, overall area and power consumption. The circuits design using CMOS logic with large number of transistotors and maximum length interconnect are increasingly the dominant contributor to delay, area and energy consumption. The use of multivalue logic with a single voltage supply and employing only simple voltage mode structures. reduces the number of interconnections with carry more information on a one line . which in turn reduces the power consumption. In this paper the multivalue logic multiplexer and decoder circuit on 50nm technology is propose. The transmission gate is use for the design of 16X1 multivalue logic multiplexer circuit. The charging time of TG is proportional to its time constant, thus to enhance the speed of circuit the switching resistance is require to decrease. The circuit is companionable with standard CMOS base circuits.

Full text: IJISM_495_Final.pdf [Bibtex]